1. Field of the Invention
The present invention pertains to the packet technology known as Asynchronous Transfer Mode (ATM), and particularly to internal routing of traffic cells through a multi-staged ATM node.
2. Related Art and Other Considerations
The increasing interest for high band services such as multimedia applications, video on demand, video telephone, and teleconferencing has motivated development of the Broadband Integrated Service Digital Network (B-ISDN). B-ISDN is based on a technology know as Asynchronous Transfer Mode (ATM), and offers considerable extension of telecommunications capabilities.
ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and traditionally have a fixed size. A traditional ATM cell comprises 53 octets, five of which form a header and forty eight of which constitute a xe2x80x9cpayloadxe2x80x9d or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
At its termination points, an ATM network is connected to terminal equipment, e.g., ATM network users. Typically between ATM network termination points there are plural switching nodes, the switching nodes having ports which are connected together by physical transmission paths or links. Thus, in traveling from an originating terminal equipment to a destination terminal equipment, ATM cells forming a message may travel through several switching nodes.
A switching node has a plurality of ports, each of which can be connected by via a link circuit and a link to another node. The link circuit performs packaging of the cells according to the particular protocol in use on the link. A cell incoming to a switching node may enter the switching node at a first port and exit from a second port via a link circuit onto a link connected to another node. Each link can carry cells for plural connections, a connection being e.g., a transmission between a calling subscriber or party and a called subscriber or party.
The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially functions like a cross-connect between ports of the switch. Paths internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a message ultimately to travel from an ingress side of the switch to an egress side of the switch. The ports of the switch core are connected to interface modules which can reside on device boards. The interface modules serve to interface the switch core with one or more devices also residing on the device board, such devices being (for example) processors, an AAL or ATM termination unit, or an exchange terminal (ET). Some of these devices can be connected to external links, such as (for example) an exchange terminal (ET) connects the ATM node to another ATM node via an external link. For functions such as a conversion operation hereinafter described, the exchange terminals typically have processors (known as xe2x80x9cboard processorsxe2x80x9d or xe2x80x9cBPsxe2x80x9d) mounted thereon.
Typically an ATM switch core and its connected device boards [upon which the interface modules and devices such as exchange terminals (ET) are mounted] reside together on one subrack of a rack of electronic components. When a connection is to be set up involving the ATM node, a connection set up operation is performed. Thereafter, while the connection is set up, ATM cells are received at the ATM node on a particular external link. When an ATM cell is received, the board processor BP on the device board which is connected to the receiving external link consults conversion tables maintained by the board processor. From the conversion tables the board processor determines a mapping from, e.g., the external VPI/VCI values (from the header of the ATM cell received on the external link) to internal VPI/VCI values. The internal VPI/VCI is used for routing the payload of the received cell through the ATM node, and particularly through its switch core. After the cell is routed through the ATM node, a similar conversion process is performed at the device board from which the cell is to leave the ATM node. That is, another conversion process uses the internal VPI/VCI to prepare another external VPI/VCI to insert in the header of an outgoing cell as it leaves the ATM node.
The conversion tables utilized for the VPI/VCI conversions are communicated or updated to the board processors at connection set up from by a main processor of the node. The main processor can reside, for example, on one of the device boards of the node. An internal control path (ICP) is required to connect the main processor to each of the board processors (BPs) which perform VPI/VCI conversion operations.
There are envisioned larger ATM nodes comprising, for example, multiple subracks with one of the subracks acting as a main switch (e.g., a xe2x80x9cgroup switchxe2x80x9d in some parlance). For example, the subracks (each constituting a stage of the overall node) can be connected in cascading fashion to form a multi-staged ATM node. The conversion process described above can be employed in such larger modes. Consider, for example, a three stage ATM node comprising three subracks, with a second of the subracks functioning as the main switch and being connected between the first and third subracks. In such three stage ATM node, the routing of a cell through the node in accordance with the conversion procedure described above requires two conversion operations at each subrack (one conversion operation upon ingress; another conversion operation upon egress), for a total of six conversions. Moreover, upon setting up a connection from, e.g., a device/ET in one subrack to a device/ET in another subrack requires setting up the conversion tables for all exchange terminals (ETs) of the involved internal ET links (i.e., the links interconnecting the main switch along the path of the connection). Such connection set up involves more internal control paths (ICPs) and essentially increases connection set up time by a factor of three.
What is needed, therefore, and an object of the present invention, is a technique for internally routing ATM cells through a multi-staged ATM node.
An internal routing tag is appended to a payload of an ATM cell for routing the ATM cell through a multi-stage ATM node. The routing tag comprises routing information for routing the payload of the received ATM cell through plural stages of the multi-stage node. Preferably the routing information comprises a list of destination addresses, e.g., utopia address of physical units in the multi-stage ATM node. In an illustrated embodiment, the multi-stage ATM node has stages, each stage being situated on a subrack. Each stage or subrack of the multi-stage node comprises a switch core connected to a first set of interface units and a second set of interface units. For such embodiment, the routing tag includes, as the destination addresses, physical addresses for one of the first set of interface units and one of the second set of interface units for each stage of the multi-stage node. The interface units can be, for example, switch port interface modules (SPIM).
A connection set up request is forwarded to a connection setup manager which preferably resides at a main processor of the multi-stage ATM node. The connection setup manager responds by providing transfer lists for the connection to two tagging units BP/TUs. The two tagging units BP/TUs which receive transfer lists are on device boards connected to the two external links involved in the connection. The transfer list is a list of destination addresses to be used for switching and routing of the traffic cell through the multi-stage ATM node. The transfer list received by one of the two tagging units BP/TUs is used for routing cells in one direction through the multi-stage ATM node; the transfer list received by the other of the two tagging units BP/TUs is used for routing cells in a reverse direction through the multi-stage ATM node. The transfer lists are written into conversion tables of the two tagging units BP/TUs. After connection setup, when an ATM cell participating in the connection is received from an external link, a tagging unit BP/TU obtains the VPI/VCI and link identifier from the header of the incoming ATM cell. Using these parameters, the tagging unit BP/TU consults its conversion table to obtain the transfer list for the cell. Two other parameters, specifically cell size and QoS indicator, are also added to form the internal routing tag or xe2x80x9cSPAS tagxe2x80x9d.
In an illustrated embodiment, the transfer list of the SPAS tag includes six octets, each octet including, e.g., a destination address for routing through the multi-stage ATM node. As a cell is routed through the multi-stage ATM node, units which receive the cell analyze and, where appropriate, operate on the top octet in the transfer list. These operations including, as a top octet is utilized in route to or at a unit having the destination address thereof, exchanging the destination address with a source address from whence the cell came; changing the parity of the octet from odd to even; and, popping the octet so that it goes to the bottom of the transfer list. The popping of the octet leaves another octet on top of the transfer list, that another octet containing the next destination address to which the cell is to be routed.
Formats of SPAS tags are provided for accommodating ATM packets of various protocols, including an AAL2xe2x80x2 protocol and an AAL2xe2x80x3 protocol, as well as for various Utopia devices (e.g., eight bit and sixteen bit). For multi-stage ATM nodes having a ring or bus topology, an octet pair is included in SPAS tag for routing the cell on the ring or bus.
Use of the internal routing tag streamlines connection setup, reduces the number of internal control paths required, and obviates VPI/VCI conversion at the plural stages of the multi-stage node.